MATCFG=MATCFG_0, AUTOSTOP=AUTOSTOP_0, TIMECFG=TIMECFG_0, IGNACK=IGNACK_0, PRESCALE=PRESCALE_0, PINCFG=PINCFG_0
Master Configuration Register 1
| PRESCALE | Prescaler 0 (PRESCALE_0): Divide by 1 1 (PRESCALE_1): Divide by 2 2 (PRESCALE_2): Divide by 4 3 (PRESCALE_3): Divide by 8 4 (PRESCALE_4): Divide by 16 5 (PRESCALE_5): Divide by 32 6 (PRESCALE_6): Divide by 64 7 (PRESCALE_7): Divide by 128 |
| AUTOSTOP | Automatic STOP Generation 0 (AUTOSTOP_0): No effect 1 (AUTOSTOP_1): STOP condition is automatically generated whenever the transmit FIFO is empty and the LPI2C master is busy |
| IGNACK | IGNACK 0 (IGNACK_0): LPI2C Master will receive ACK and NACK normally 1 (IGNACK_1): LPI2C Master will treat a received NACK as if it (NACK) was an ACK |
| TIMECFG | Timeout Configuration 0 (TIMECFG_0): Pin Low Timeout Flag will set if SCL is low for longer than the configured timeout 1 (TIMECFG_1): Pin Low Timeout Flag will set if either SCL or SDA is low for longer than the configured timeout |
| MATCFG | Match Configuration 0 (MATCFG_0): Match is disabled 2 (MATCFG_2): Match is enabled (1st data word equals MATCH0 OR MATCH1) 3 (MATCFG_3): Match is enabled (any data word equals MATCH0 OR MATCH1) 4 (MATCFG_4): Match is enabled (1st data word equals MATCH0 AND 2nd data word equals MATCH1) 5 (MATCFG_5): Match is enabled (any data word equals MATCH0 AND next data word equals MATCH1) 6 (MATCFG_6): Match is enabled (1st data word AND MATCH1 equals MATCH0 AND MATCH1) 7 (MATCFG_7): Match is enabled (any data word AND MATCH1 equals MATCH0 AND MATCH1) |
| PINCFG | Pin Configuration 0 (PINCFG_0): 2-pin open drain mode 1 (PINCFG_1): 2-pin output only mode (ultra-fast mode) 2 (PINCFG_2): 2-pin push-pull mode 3 (PINCFG_3): 4-pin push-pull mode 4 (PINCFG_4): 2-pin open drain mode with separate LPI2C slave 5 (PINCFG_5): 2-pin output only mode (ultra-fast mode) with separate LPI2C slave 6 (PINCFG_6): 2-pin push-pull mode with separate LPI2C slave 7 (PINCFG_7): 4-pin push-pull mode (inverted outputs) |